;----------------------------------------------------------------------
;	PEGASUS[2A] : MSB-98 in [K4r] ROM Grains (2theta-5theta)
;----------------------------------------------------------------------
a_or_b		equ	0	;  <---   [2A] = 0 / [2B] = 1

;========== Data Area =====================================
	dseg    abs d_area(04000h)
rx_fifo:	ds      256*16  ; MIDI RX FIFO (7000-7FFF)
tx_fifo:	ds      256*16  ; MIDI TX FIFO (8000-8FFF)
	iseg    abs i_area(0ff00h)
fnum_l:		ds	1	; DSP-01 Offset 00h
fnum_m:		ds	1	;               10h
fnum_h:		ds	1	;               20h
start_pt:	ds	1	;               30h
loop_top:	ds	1	;               40h
loop_end:	ds	1	;               50h
bank:  		ds	1	;               60h
attack_lev:	ds	1	;               a0h
attack_sp: 	ds	1	;               b0h
decay_lev:	ds	1	;               c0h
decay_sp: 	ds	1	;               d0h
bank_port_l:	ds	1	;
bank_port_h:	ds	1	;
sense:		ds	1	; Pitch Sense
select:		ds	1	; [0]=2/3-theta [1]=4/5-theta
wave_sel:	ds	1	; 0 - 1F
wave_comp:	ds	1	; 0 - 1F
pitch:		ds	1	; Pitch 
volume:		ds	1	; Volume Data
pan:		ds	1	; Panpot Data
cf_flag:	ds      1       ;
df_flag:	ds      1       ;
int_flg:	ds      1       ; Interrupt Check Flags
rx_data:        ds      1       ; MIDI Received 1 Byte Data Buffer
rx_top:	 	ds      2       ; MIDI Receive FIFO Top Pointer
rx_end:	 	ds      2       ; MIDI Receive FIFO End Pointer
channel:    	ds      1       ; MIDI Channel Buffer
rsb:		ds      1       ; Running Status Buffer
dcb:		ds      1       ; Data Count Buffer
data_1st:   	ds      1       ; DSP-01 Received 1 Byte Data Buffer
data_2nd:   	ds      1       ; DSP-01 Received 1 Byte Data Buffer
end_mark:       ds      3       ; Use for Debug !

;========== Port Defines Area =============================
dsp-01	  	equ     0fa00h  ; Tone Generator [DSP-01] : FA00-FBFF
internal_ram    equ     0fdc0h  ; Internal RAM Top Address
port_p01cr      equ     0ffc2h  ; Port 0/1 Control
port_p2cr       equ     0ffc5h  ; Port-2 Control
port_iop3       equ     0ffc6h  ; Port-3
port_p3cr       equ     0ffc7h  ; Port-3 Control
port_p4cr       equ     0ffc9h  ; Port-4 Control
port_iop5       equ     0ffcah  ; Port-5
port_smmod      equ     0ffcbh  ; Stepping Motor Mode
port_iop6       equ     0ffcch  ; Port-6
port_iop7       equ     0ffcdh  ; Port-7
port_p67cr      equ     0ffceh  ; Port-6/7 Control
port_iop8       equ     0ffd0h  ; Port-8
port_p8cr       equ     0ffd1h  ; Port-8 Control
port_wdmod      equ     0ffd2h  ; Watch Dog Timer Mode
port_wdcr       equ     0ffd3h  ; Watch Dog Timer Control
port_treg0      equ     0ffd4h  ; 16bit Timer <0/1>
port_treg2      equ     0ffd6h  ; 8bit Timer <2>
port_treg3      equ     0ffd7h  ; 8bit Timer <3>
port_tclk       equ     0ffd8h  ; Timer Source Control
port_tmod       equ     0ffdah  ; Timer Mode
port_trun       equ     0ffdbh  ; Timer/Serial Baud Rate
port_treg5      equ     0ffe2h  ; 16bit Timer <5> [low]
port_t4mod      equ     0ffe4h  ; 16bit Timer Mode
port_t4ffcr     equ     0ffe5h  ; 16bit Timer Control
port_intel      equ     0ffe6h  ; Interrupt Enable Mask [low]
port_inteh      equ     0ffe7h  ; Interrupt Enable Mask [high]
port_dmaeh      equ     0ffe8h  ; Micro DMA Enable Mask [high]
port_scmod      equ     0ffe9h  ; Serial Channel Mode
port_sccr       equ     0ffeah  ; Serial Channel Control
port_scbuf      equ     0ffebh  ; Serial Channel Buffer
port_bx	 	equ     0ffech  ; Bank Register x
port_by	 	equ     0ffedh  ; Bank Register y
port_adreg      equ     0ffeeh  ; A/D Converter Data Buffer
port_admod      equ     0ffefh  ; A/D Converter Control
port_option_x   equ     0fff0h  ; DSR Bit : [Read] --> Active [Low]
port_option_y   equ     0fff1h  ; DRR Bit : [Read] --> Active [Low]
port_option_z   equ     0fff2h  ; CLR DRR : [Read] --> Clear INT0
port_option_d   equ     0fff3h  ; CLR DSR : Initial=[Read]
port_rs232c     equ     0fff8h  ; External UART(1) --> INT1
port_ex_midi    equ     0fffah  ; External UART(2) --> INT2
port_data       equ     0fffch  ; MPU Data Get Port (RD) : INT0
port_command    equ     0fffdh  ; MPU Command Get Port (RD) : INT0
port_send       equ     0fffeh  ; MPU Data Send Port (WR)
port_system     equ     0ffffh  ; System Port (WR) 6bit

;========== Bit Map Defines Area ==========================
int_bit_midi    equ     0       ; Int_Flg       ; MIDI

;========== MACRO Defines =================================
%define(reset_013)(
	ld	a,(port_option_x)	 ; DSR Clear
	ld	a,(port_option_y)	 ; DRR Clear
	ld	a,(port_option_z)	 ; INT Clear
	ld	a,(port_option_d)	 ; DSR F/F Clear
	ld	(port_option_z),00000000b ;
	ld	(port_option_y),00000000b ;
	ld	(port_option_x),00001000b ; MIDI Gate ON
	)
%define(dsp-01_system(offset,data))(
	ld	(dsp-01+%offset),%data
	nop
	ld	(dsp-01+0f3h),%data
	nop
	)

;========== Head Program Area =============================
	cseg    abs c_area(0)
	di
	ld	sp,0ffc0h
	call    system_setup	    ; System Initialize --> Main Loop
	jp	main_loop

;========== Interrupt Vector/Sequence =====================
	org     10h		     ; Software Interrupt : SWI
	reti
	org     18h		     ; Non Mascable Interrupt : NMI
	reti
	org     20h		     ; Watch Dog Timer : INTWD
	reti
	org     28h		     ; External Interrupt #0 : INT0
	reti
	org     30h		     ; Timer Interrupt #0 : INTT0
	reti
	org     38h		     ; Timer Interrupt #1 : INTT1
	reti
	org     40h		     ; Timer Interrupt #2 : INTT2
	reti
	org     48h		     ; Timer Interrupt #3 : INTT3
	reti
	org     50h		     ; Timer Interrupt #4 : INTT4
	reti
	org     58h		     ; External Interrupt #1 : INT1
	reti
	org     60h		     ; Timer Interrupt #5 : INTT5
	reti
	org     68h		     ; External Interrupt #2 : INT2
	reti
	org     70h		     ; UART Receive Interrupt : INTRX
	push    hl
	push    bc
	jr	_int_midi_rx
	org     78h		     ; UART Transmit Interrupt : INTTX
	set     int_bit_midi,(int_flg)
	reti
_int_midi_rx:
	ld	hl,(rx_top)
	ld	bc,rx_fifo
	add     hl,bc
	ld	a,(port_scbuf)
	cp	a,0feh
	jr	z,_int_rx_ex
	ld	(hl),a
	incw    (rx_top)
	bit     4,(rx_top+1)
	jr	z,_int_rx_ex
	ldw     (rx_top),0
_int_rx_ex:
	pop     bc
	pop     hl
	reti

;========== System Initialize Routine =====================
system_setup:
	%reset_013
;<< DSP-01 Initialize >>
	ld	(port_iop3),11111011b   ; DSP-01 Reset !
	ld	bc,07fffh
_wait_loop:
	nop
	djnz    bc,_wait_loop
	ld	(port_iop3),11111111b   ; DSP-01 Start !
;<< CPU : TMP91C640 Initialize >>
	ld	(port_wdmod),01110000b  ; Watch Dog OFF
	ld	(port_wdcr),0b1h	; Watch Dog OFF
	ld	(port_intel),01011111b  ; Interrupt Enable
	ld	(port_inteh),00000101b  ; Interrupt Enable
	ld	(port_dmaeh),00000000b  ; Micro DMA Disable
	ld	(port_p01cr),00000110b  ; Port 0/1 = Data/Address Bus
	ld	(port_p2cr),11111111b   ; Port 2 = Address Bus
	ld	(port_p3cr),10101001b   ; Port 3 = UART
	ld	(port_sccr),00000000b   ; Port 3 = Constant
	ld	(port_p4cr),00001111b   ; Port 4 = Bank Address
	ld	(port_smmod),00000000b  ; Port 6/7 = Port
	ld	(port_p67cr),11111111b  ; Port 6/7 = Output
	ld	(port_p8cr),00001000b   ; Port 8 = Output/Buzzer
	ld	(port_scmod),00101000b  ; UART Control
	ld	(port_trun),10101111b   ; Baud Rate
	ld	(port_tmod),00000100b   ; 8bit Timer Mode
	ld	(port_tclk),10010001b   ; Timer Assign
	ld	(port_t4mod),00000110b  ; 16bit Timer Mode
	ld	(port_t4ffcr),00001011b ; 16bit Timer Control
	ldw     (port_treg0),0ffffh     ; (dummy) Tempo
	ld	(port_treg2),3	  	; MIDI Divide Rate : 12MHz
	ld	(port_treg3),187	; 1msec Interval Constant(1)
	ld	(port_admod),0f0h       ; A/D Wait
	ld	(port_bx),00h	   	; ROM/RAM Area
	ld	(port_by),00h	   	;
;<< RAM Area Initialize >>
	ld	hl,internal_ram	 	; Internal RAM Area
	ld	bc,512-16
_int_ram_clear:
	ld	(hl),0
	inc     hl
	djnz    bc,_int_ram_clear
	ld	(cf_flag),0
	ld	(df_flag),0
	ld	(fnum_l),0ffh
	ld	(start_pt),0
	ld	(pitch),64
	ld	(sense),040h
	call	dsp-01_pitch
	ld	(loop_top),0
	ld	(loop_end),100
	call	dsp-01_loop
	ld	(select),0		; lower-theta
	ld	(wave_sel),10h
	ld	(wave_comp),10h
	ld	(pan),40h
	call	dsp-01_bk_pan
	ld	(attack_lev),00fh
	ld	(attack_sp),00fh
	call	dsp-01_attack
	ld	(volume),0
	ld	(decay_sp),00fh
	call	dsp-01_decay
	call	dsp-01_off
	call	dsp-01_on
	%dsp-01_system(0f5h,0)	  	; Memory Bus Close
	%dsp-01_system(0f0h,0)	  	; Random Bit Pattern
	%dsp-01_system(0f2h,00100000b)  ; Output Parameter
	%dsp-01_system(0f5h,1)	  	; Memory Bus Open
	%reset_013
	ld	a,(port_scbuf)	  	;
	ei			      	;
	ret

;========== DSP-01 Setting ================================
send_loop:
	ld	a,16
_set_loop:
	ld	(bc),l
	nop
	nop
	ld	(de),h
	inc	bc
	inc	de
	dec	a
	cp	a,0
	jp	nz,_set_loop
	ret
dsp-01_pitch:
	ld	l,(pitch)
	mul	hl,(sense)
	ld	(fnum_m),l
	ld	(fnum_h),h
	ld	l,(fnum_l)
	ld	h,(fnum_m)
	ld	bc,dsp-01+000h
	ld	de,dsp-01+010h
	call	send_loop
	ld	l,(fnum_h)
	ld	h,(start_pt)
	ld	bc,dsp-01+020h
	ld	de,dsp-01+030h
	call	send_loop
	ret
dsp-01_loop:
	ld	a,(loop_end)
	xor	a,0ffh
	and	a,01111111b
	ld	hl,loop_end_table
	ld	h,(hl+a)
	ld	l,(loop_top)
	ld	bc,dsp-01+040h
	ld	de,dsp-01+050h
	cp	h,70h
	jr	c,_lend_pass
	ld	h,70h
_lend_pass:
	ld	a,16
_set_lend:
	ld	(bc),l
	nop
	nop
	ld	(de),h
	inc	bc
	inc	de
	inc	h
	dec	a
	cp	a,0
	jr	nz,_set_lend
	ret
loop_end_table:
	db	1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23
	db	24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43
	db	44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63
	db	040h,042h,044h,046h,048h,04ah,04ch,04eh		; 40-47
	db	050h,052h,054h,056h,058h,05ah,05ch,05eh		; 48-4F
	db	060h,062h,064h,066h,068h,06ah,06ch,06eh		; 50-57
	db	070h,073h,076h,079h,07ch,07fh,082h,085h		; 58-5F
	db	088h,08bh,08eh,092h,096h,09ah,09eh,0a3h		; 60-67
	db	0a7h,0abh,0afh,0b3h,0b7h,0bbh,0bfh,0c3h		; 68-6F
	db	0c7h,0cbh,0cfh,0d3h,0d7h,0dbh,0dfh,0e3h		; 70-77
	db	0e7h,0ebh,0efh,0f3h,0f7h,0fbh,0ffh,0ffh,0ffh	; 78-7F
dsp-01_bk_pan:
	ld	(bank),0c0h
	bit	0,(select)
	jr	z,_bk_pan_1
	ld	(bank),0
_bk_pan_1:
	ld	a,(wave_sel)
	srla
	ld	(port_iop7),a
	ld	a,(wave_comp)
	srla
	srla
	ld	(port_iop6),a
	bit	0,(wave_sel)
	jr	z,_bk_pan_2
	set	3,(port_iop6)
_bk_pan_2:
	bit	1,(wave_comp)
	jr	z,_bk_pan_3
	set	2,(bank)
_bk_pan_3:
	bit	0,(wave_comp)
	jr	z,_bk_pan_4
	set	0,(bank)
_bk_pan_4:
	ld	a,(pan)
	bit	6,a
	jr	z,_bk_pan_minus
	sub	a,040h
	slaa
	jr	_bk_pan_mix
_bk_pan_minus:
	xor	a,0ffh
	slaa
	or	a,10000000b
_bk_pan_mix:
	ld	h,a
	ld	l,(bank)
	ld	bc,dsp-01+060h
	ld	de,dsp-01+070h
	call	send_loop
	ret
dsp-01_attack:
	ld	l,(attack_lev)
	ld	h,(attack_sp)
	ld	bc,dsp-01+0a0h
	ld	de,dsp-01+0b0h
	call	send_loop
	ret
dsp-01_decay:
	ld	a,(volume)
	srla
	ld	hl,_speed_table
	ld	l,(hl+a)
	ld	h,(decay_sp)
	ld	bc,dsp-01+0c0h
	ld	de,dsp-01+0d0h
	call	send_loop
	ret
_speed_table:
        db      0f1h,08fh,07fh,06ch,06fh,05ch,05fh,04ch
        db      04fh,038h,039h,03ah,03bh,03ch,03dh,03eh
        db      03fh,028h,029h,02ah,02bh,02ch,02dh,02eh
        db      02fh,02fh,018h,018h,019h,019h,01ah,01ah
        db      01bh,01bh,01ch,01ch,01dh,01dh,01eh,01eh
        db      01fh,01fh,008h,008h,009h,009h,009h,00ah
        db      00ah,00ah,00bh,00bh,00bh,00ch,00ch,00ch
        db      00eh,00eh,00eh,00eh,00fh,00fh,00fh,00fh
dsp-01_on:
	ld	hl,dsp-01+090h
	ld	a,0
_on_loop:
	ld	(hl+a),3
	inc	a
	cp	a,16
	jr	nz,_on_loop
	ret
dsp-01_off:
	ld	hl,dsp-01+090h
	ld	a,0
_off_loop:
	ld	(hl+a),0
	inc	a
	cp	a,16
	jr	nz,_off_loop
	ret

;========== Main Loop =====================================
main_loop:
	call    midi_rx_check
	jr	main_loop

;========== MIDI Received Data Check ======================
midi_rx_check:
	ld	hl,(rx_end)
	cp	hl,(rx_top)	     	; FIFO Event ?
	ret     z
	ld	de,rx_fifo
	add     hl,de
	ld	b,(hl)
	ld	(rx_data),b
	incw    (rx_end)
	bit     4,(rx_end+1)
	jr	z,_rx_midi_nx
	ldw     (rx_end),0
_rx_midi_nx:
	bit     7,b
	jr	z,running
	cp	b,0f8h
	ret     nc		      	; Realtime = Pass !
	cp	b,0f0h
	jr	c,status
	ld	(rsb),0	     		; [F0]-[F7] = Pass !
	ret
status:
	ld	a,b
	and     b,11110000b
	ld	(rsb),b
	and     a,00001111b
	ld	(channel),a
	ld	(dcb),0
	ret
running:
	ld	a,(rsb)
	cp	a,0
	ret     z
	cp	(dcb),0
	jr	nz,_run_2nd
	ld	(data_1st),b
	cp	a,0c0h
	jp	z,prog_change
	cp	a,0d0h
	jp	z,ch_pressure
	ld	(dcb),1
	ret
_run_2nd:
	ld	(data_2nd),b
	ld	(dcb),0
	cp	(rsb),0a0h
	ret	nz
	cp	(channel),0fh
	jp	z,pressure
	ret

pressure:
	ld	a,(data_1st)
	cp	a,10+a_or_b*10		; %%%
	jr	z,_sel_set
	cp	a,11+a_or_b*10		; %%%
	jr	z,_sense_set
	cp	a,12+a_or_b*10		; %%%
	jr	z,_cf_setting
	cp	a,13+a_or_b*10		; %%%
	jr	z,_df_setting
	cp	a,14+a_or_b*10		; %%%
	jr	z,_wave_sel_set
	cp	a,15+a_or_b*10		; %%%
	jr	z,_wave_comp_set
	cp	a,16+a_or_b*10		; %%%
	jr	z,_loop_set
	cp	a,17+a_or_b*10		; %%%
	jr	z,_pitch_set
	cp	a,18+a_or_b*10		; %%%
	jr	z,_volume_set
	cp	a,19+a_or_b*10		; %%%
	jr	z,_panpot_set
	ret
_sel_set:
	ld	a,(data_2nd)
	ld	(select),a
	call	dsp-01_bk_pan
	ret
_sense_set:
	ld	a,(data_2nd)
	ld	(sense),a
	call	dsp-01_pitch
	ret
_cf_setting:
	ld	a,(data_2nd)
	ld	(cf_flag),a
	ret
_df_setting:
	ld	a,(data_2nd)
	ld	(df_flag),a
	ret
_wave_sel_set:
	ld	a,(data_2nd)
jump_select:
	xor	a,0ffh
	and	a,01111111b
	srla
	srla
	ld	(wave_sel),a
	call	dsp-01_bk_pan
	ret
_wave_comp_set:
	ld	a,(data_2nd)
jump_compress:
	xor	a,0ffh
	and	a,01111111b
	srla
	srla
	ld	(wave_comp),a
	call	dsp-01_bk_pan
	ret
_loop_set:
	ld	a,(data_2nd)
jump_loop:
	ld	(loop_end),a
	call	dsp-01_loop
	ret
_pitch_set:
	ld	a,(data_2nd)
jump_pitch:
	ld	(pitch),a
	call	dsp-01_pitch
	ret
_volume_set:
	ld	a,(data_2nd)
jump_volume:
	ld	(volume),a
	call	dsp-01_decay
	ret
_panpot_set:
	ld	a,(data_2nd)
jump_panpot:
	ld	(pan),a
	call	dsp-01_bk_pan
	ret

prog_change:
	cp	(channel),0fh
	ret	nz
	cp	(cf_flag),0
	ret	z
	ld	a,(cf_flag)
	jr	_cf_df_mix
ch_pressure:
	cp	(channel),0fh
	ret	nz
	cp	(df_flag),0
	ret	z
	ld	a,(df_flag)
_cf_df_mix:
	dec	a
	slaa
	ld	hl,jump_table
	ld	hl,(hl+a)
	ld	a,(data_1st)
	jp	hl
jump_table:
	dw	jump_select
	dw	jump_compress
	dw	jump_loop
	dw	jump_pitch
	dw	jump_volume
	dw	jump_panpot

	end