;-----------------------------------------------------------------------
;	[PEGASUS-5] MIDI Merge / Video Control Box : December.1993
;-----------------------------------------------------------------------

;##### RAM Map #####
	dseg
	org	0000h
rx_fifo_0	ds	4096
rx_fifo_1	ds	4096
rx_fifo_2	ds	4096
rx_fifo_3	ds	4096
tx_fifo_0	ds	4096
tx_fifo_1	ds	4096
tx_fifo_2	ds	4096
rx_top_0	ds	2
rx_end_0	ds	2
rx_top_1	ds	2
rx_end_1	ds	2
rx_top_2	ds	2
rx_end_2	ds	2
rx_top_3	ds	2
rx_end_3	ds	2
tx_top_0	ds	2
tx_end_0	ds	2
tx_top_1	ds	2
tx_end_1	ds	2
tx_top_2	ds	2
tx_end_2	ds	2
rx_data		ds	4
rsb		ds	4
dcb		ds	4
channel		ds	4
keyno		ds	4
cg_note		ds	1
cg_velocity	ds	1
power_timer	ds	2
led_timer	ds	8
led_mode	ds	1
led_data	ds	1
glove_tim	ds	1
glove_old	ds	1

;##### I/O Map #####
	cseg
sio_a		equ	0018h	; for Glove Rx
sio_b		equ	001ah	; for Glove Rx
pio_a		equ	001ch
pio_b		equ	001eh
uart_0		equ	0080h
uart_1		equ	0084h
uart_2		equ	0088h
uart_3		equ	008ch

;##### MACRO #####
all_out	macro	@1
	ld	a,@1
	out	(uart_0+1),a
	out	(uart_1+1),a
	out	(uart_2+1),a
	out	(uart_3+1),a
	endm
pio_set	macro	@1,@2
	ld	a,@2
	out	(@1+1),a
	endm
io_set	macro	@1,@2
	ld	a,@2
	out	(@1+1),a
	endm
io_put	macro	@1,@2
	ld	a,@2
	out	(@1+0),a
	endm
led_res	macro	@1
	ld	a,(led_timer+@1)
	cp	0
	ret	z
	dec	a
	ld	(led_timer+@1),a
	ret	nz
	ld	a,(led_data)
	res	@1,a
	ld	(led_data),a
	call	led_disp
	ret
	endm
led_set	macro	@1
	ld	a,20
	ld	(led_timer+@1),a
	ld	a,(led_data)
	set	@1,a
	ld	(led_data),a
	call	led_disp
	endm
rx_set	macro	@1,@2,@3
	ld	de,(@3)
	ld	a,@1
	or	d
	ld	h,a
	ld	l,e
	in	a,(@2+0)
	ld	(hl),a
	inc	de
	res	4,d
	ld	(@3),de
	ret
	endm
tx_set	macro	@1,@3
	ld	de,(@3)
	ld	a,@1
	or	d
	ld	h,a
	ld	l,e
	ld	(hl),b
	inc	de
	res	4,d
	ld	(@3),de
	ret
	endm
tx_chk	macro	@1,@2,@3,@4
	in	a,(@4+1)
	bit	0,a
	ret	z
	ld	de,(@2)
	ld	hl,(@1)
	and	a			; CY <-- 0
	sbc	hl,de
	ret	z
	ld	a,@3
	or	d
	ld	h,a
	ld	l,e
	ld	a,(hl)
	out	(@4),a
	inc	de
	res	4,d
	ld	(@2),de
	ret
	endm
rx_chk	macro	@1,@2,@3,@4
	ld	de,(@2)
	ld	hl,(@1)
	and	a			; CY <-- 0
	sbc	hl,de
	ret	z
	ld	a,@3
	or	d
	ld	h,a
	ld	l,e
	ld	b,(hl)			; [B] = Rx Data
	inc	de
	res	4,d
	ld	(@2),de
	bit	7,b
	jr	z,50$			; running
	ld	a,b
	cp	0f8h
	ret	nc
	cp	0f0h
	jr	c,20$
	xor	a
	ld	(rsb+@4),a
	ret
20$:
	led_set	@4+4
	ld	a,b
	and	11110000b
	ld	(rsb+@4),a
	xor	a
	ld	(dcb+@4),a
	ret
50$:
	led_set	@4+4
	ld	a,(rsb+@4)
	cp	0
	ret	z
	cp	0c0h
	jr	z,70$
	cp	0d0h
	jr	z,70$
	ld	a,(dcb+@4)
	cp	0
	jr	nz,90$
	inc	a
	ld	(dcb+@4),a
	ld	a,b
	ld	(keyno+@4),a
	ret
70$:
	ld	c,b
	ld	a,(rsb+@4)
	or	0fh
	ld	b,a
	call	tx_fifo_set_0
	ld	b,c
	call	tx_fifo_set_0
	led_set	7
	ret
90$:
	xor	a
	ld	(dcb+@4),a
	ld	c,b
	ld	a,(rsb+@4)
	or	0fh
	ld	b,a
	call	tx_fifo_set_0
	ld	a,(keyno+@4)
	ld	b,a
	call	tx_fifo_set_0
	ld	b,c
	call	tx_fifo_set_0
	led_set	7
	ret
	endm

;##### RESET #####
	org	0000h
	ld      sp,0ffffh
	di
	im      1
	call    initialize
	ei
	jp      loop

;##### INT / NMI #####
	org     0038h
	ex	af,af'
	exx
	call	int_sequence
	exx
	ex	af,af'
	ei
	reti
	org     0066h
	ei
	retn
int_sequence:
	in	a,(uart_3+1)
	bit	1,a
	jr	z,_next_1
	rx_set	10110000b,uart_3,rx_top_3
_next_1:
	in	a,(uart_1+1)
	bit	1,a
	jr	z,_next_2
	rx_set	10010000b,uart_1,rx_top_1
_next_2:
	in	a,(uart_2+1)
	bit	1,a
	jr	z,_next_3
	rx_set	10100000b,uart_2,rx_top_2
_next_3:
	in	a,(uart_0+1)
	bit	1,a
	ret	z
	rx_set	10000000b,uart_0,rx_top_0

;##### MIDI Transmit Data Set : Input=[B] #####
tx_fifo_set_0:
	tx_set	11000000b,tx_top_0
tx_fifo_set_1:
	tx_set	11010000b,tx_top_1
tx_fifo_set_2:
	tx_set	11100000b,tx_top_2

;##### MIDI Transmit Check #####
tx_check_0:
	tx_chk	tx_top_0,tx_end_0,11000000b,uart_0
tx_check_1:
	tx_chk	tx_top_1,tx_end_1,11010000b,uart_1
tx_check:
	tx_chk	tx_top_2,tx_end_2,11100000b,uart_2

;##### MIDI Receive Check #####
rx_fifo_0_check:
	rx_chk	rx_top_0,rx_end_0,10000000b,0
rx_fifo_1_check:
	rx_chk	rx_top_1,rx_end_1,10010000b,1
rx_fifo_2_check:
	rx_chk	rx_top_2,rx_end_2,10100000b,2
rx_fifo_3_check:
	ld	de,(rx_end_3)
	ld	hl,(rx_top_3)
	and	a			; CY <-- 0
	sbc	hl,de
	ret	z
	ld	a,10110000b
	or	d
	ld	h,a
	ld	l,e
	ld	b,(hl)			; [B] = Rx Data
	inc	de
	res	4,d
	ld	(rx_end_3),de
	bit	7,b
	jr	z,50$			; running
	ld	a,b
	cp	0f8h
	ret	nc
	cp	0f0h
	jr	c,20$
11$:
	xor	a
	ld	(rsb+3),a
	ret
20$:
	ld	a,b
	and	00001111b
	cp	0fh			; !! [F] Channel Only !!
	jr	nz,11$			; !!!!!!!!!!!!!!!!!!!!!!
	ld	(channel+3),a
	ld	a,b
	and	11110000b
	ld	(rsb+3),a
	xor	a
	ld	(dcb+3),a
	led_set	1
	ret
50$:
	ld	a,(rsb+3)
	cp	0
	ret	z
	cp	0c0h
	jr	z,70$
	cp	0d0h
	jr	z,70$
	ld	a,(dcb+3)
	cp	0
	jr	nz,90$
	inc	a
	ld	(dcb+3),a
	ld	a,b
	ld	(keyno+3),a
	ret
70$:
	led_set	1
	ld	c,b
	ld	a,(rsb+3)
	ld	d,a
	ld	a,(channel+3)
	or	d
	ld	b,a
	call	tx_fifo_set_0
	ld	b,c
	call	tx_fifo_set_0
	led_set	7
	ret
90$:
	led_set	1
	xor	a
	ld	(dcb+3),a
	ld	c,b
	ld	a,(rsb+3)
	ld	d,a
	ld	a,(channel+3)
	or	d
	ld	b,a
	call	tx_fifo_set_0
	ld	a,(keyno+3)
	ld	b,a
	call	tx_fifo_set_0
	ld	b,c
	call	tx_fifo_set_0
	led_set	7
	ld	a,(rsb+3)
	cp	0a0h
	ret	nz
	ld	a,(keyno+3)
	cp	96
	jp	z,hit_96
	cp	97
	jp	z,hit_97
	cp	98
	jp	z,hit_98
	cp	99
	jp	z,hit_99
	cp	100
	jp	z,hit_100
	cp	101
	jp	z,hit_101
	cp	102
	jp	z,hit_102
	ret
hit_96:
	ld	a,c
	sla	a			; !!!!! bit[0] = 71051 RESET !!!!!
	out	(pio_a+0),a		; 000000000 - 11111110
	ret
hit_97:
	ld	b,09ch
	call	tx_fifo_set_1
	ld	b,c
	call	tx_fifo_set_1
	ld	b,040h
	call	tx_fifo_set_1
	led_set	2
	ret
hit_98:
	ld	a,c
	ld	(cg_note),a
_hit_98_99:
	ld	b,09dh
	call	tx_fifo_set_2
	ld	a,(cg_note)
	ld	b,a
	call	tx_fifo_set_2
	ld	a,(cg_velocity)
	ld	b,a
	call	tx_fifo_set_2
	led_set	3
	ret
hit_99:
	ld	a,c
	ld	(cg_velocity),a
	jr	_hit_98_99
hit_100:
	ld	b,0bdh
	call	tx_fifo_set_2
	ld	b,1
	call	tx_fifo_set_2
	ld	b,c
	call	tx_fifo_set_2
	led_set	3
	ret
hit_101:
	ld	b,0edh
	call	tx_fifo_set_2
	ld	b,0
	call	tx_fifo_set_2
	ld	b,c
	call	tx_fifo_set_2
	led_set	3
	ret
hit_102:
	ret

;##### Main Program #####
loop:
	call	rx_fifo_0_check
	call	tx_check_0
	call	rx_fifo_1_check
	call	tx_check_1
	call	rx_fifo_2_check
	call	tx_check_2
	call	rx_fifo_3_check
	call	led_display
	call	glove_check
	jr	loop

;##### INITIALIZE #####
initialize:
	ld      hl,0f000h
	ld      a,0f8h
_ram_clear_loop:
	ld      (hl),0
	inc     hl
	cp      h
	jr	nc,_ram_clear_loop
	pio_set	pio_a,0cfh		; Mode 3
	pio_set	pio_a,00000000b		; 0:Out / 1:In
	pio_set	pio_a,007h		; Interrupt Disable
	ld	a,00000001b
	out	(pio_a+0),a
	call	wait_long
	ld	a,0
	out	(pio_a+0),a
	pio_set	pio_b,0cfh		; Mode 3
	pio_set	pio_b,00000000b		; 0:Out / 1:In
	pio_set	pio_b,007h		; Interrupt Disable
	ld	a,00000001b
	ld	(led_data),a
	call	led_disp
	call	wait_long
	io_set	sio_a,00011000b		; Channel Reset A
	io_set	sio_a,00000100b		; Resister Point = 4
	io_set	sio_a,00000000b		; Mode
	io_set	sio_b,00011000b		; Channel Reset B
	io_set	sio_b,00000100b		; Resister Point = 4
	io_set	sio_b,00000000b		; Mode
	io_set	sio_a,00010000b		; clear
	io_set	sio_b,00010000b		; clear
	all_out	0
	all_out	0
	all_out	0
	call	wait_long
	all_out	01000000b
	all_out	01001110b
	all_out	00000101b
	ld	a,0fch
	out	(uart_0+0),a
	out	(uart_1+0),a
	out	(uart_2+0),a
	ld	a,04ch
	ld	(cg_velocity),a
	ret
wait_long:
	ld	c,15
_wait_long_loop:
	call	wait_mid
	dec	c
	jr	nz,_wait_long_loop
	ret
wait_mid:
	ld	a,15
_wait_mid_loop:
	call	wait_short
	dec	a
	jr	nz,_wait_mid_loop
	ret
wait_short:
	db	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
	ret

;##### LED Display Routine #####
led_disp:
	ld	a,(led_data)
	xor	0ffh
	out	(pio_b+0),a
	ret
led_display:
	call	power_timer_chk
	ld	a,(led_mode)
	inc	a
	and	00000111b
	ld	(led_mode),a
	cp	1
	jp	z,led_1
	cp	2
	jp	z,led_2
	cp	3
	jp	z,led_3
	cp	4
	jp	z,led_4
	cp	5
	jp	z,led_5
	cp	6
	jp	z,led_6
	cp	7
	jp	z,led_7
	ret
led_1:
	led_res	1
led_2:
	led_res	2
led_3:
	led_res	3
led_4:
	led_res	4
led_5:
	led_res	5
led_6:
	led_res	6
led_7:
	led_res	7
power_timer_chk:
	ld	a,(power_timer+0)
	dec	a
	ld	(power_timer+0),a
	ret	nz
	ld	a,100
	ld	(power_timer+0),a
	ld	a,(power_timer+1)
	dec	a
	ld	(power_timer+1),a
	ret	nz
	ld	a,50
	ld	(power_timer+1),a
	ld	a,(led_data)
	xor	00000001b
	ld	(led_data),a
	call	led_disp
	ret

;##### Wireless Power Glove Check Routine #####
glove_check:
	ld	a,(glove_tim)
	dec	a
	ld	(glove_tim),a
	ret	nz
	ld	a,20
	ld	(glove_tim),a
	ld	e,0
	in	a,(sio_a+1)
	bit	3,a
	jr	nz,_gl_1
	set	0,e
_gl_1:
	bit	5,a
	jr	nz,_gl_2
	set	1,e
_gl_2:
	in	a,(sio_b+1)
	bit	3,a
	jr	nz,_gl_3
	set	2,e
_gl_3:
	bit	5,a
	jr	nz,_gl_4
	set	3,e
_gl_4:
	ld	a,(glove_old)
	cp	e
	ret	z
	ld	a,e
	ld	(glove_old),a
	ld	b,0afh
	call	tx_fifo_set_0
	ld	b,127
	call	tx_fifo_set_0
	ld	a,(glove_old)
	ld	b,a
	call	tx_fifo_set_0
	io_set	sio_a,00010000b		; clear
	io_set	sio_b,00010000b		; clear
	ret

	end